Clocks - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English
The following table lists the clocks that are present in the MRMAC.
Note: All datapath-related clocks are per-port. However, clocks are tied together internally in certain operating modes, and the lower-numbered port clock is used.
Table 1. Clocks
Clock Port Description
AXI4-Lite s_axi_aclk AXI4-Lite processor interface clock.
AXI tx_axi_clk[2:0]

rx_axi_clk[2:0]

AXI4-Stream interface clocks. These clocks are used by the AXI4-Stream interface when in independent clock mode. They are also used by certain timestamping signals, and a number of device statistics and flow control signals. The clocks are shared between two ports of the MRMAC. The tx_axi_clk[0] and rx_axi_clk[0] are shared between Ports 0 and 1, The tx_axi_clk[2] and rx_axi_clk[2] are shared between Ports 2 and 3.
core tx_core_clk[3:0]

rx_core_clk[3:0]

Per-port high-speed clocks which drive the MRMAC internals.
serdes rx_serdes_clk[3:0] Per-port high-speed clocks for the GT interface.
For RX side:
  • Narrow mode, rx_serdes_clk[3:0] is used.
  • Wide mode rx_alt_serdes_clk[3:0] is used.
For TX side:
  • Narrow mode, tx_core_clk[3:0] is used.
  • Wide mode tx_alt_serdes_clk[3:0] is used.
Ts tx_ts_clk[3:0]

rx_ts_clk[3:0]

Per-port clocks for the timestamp interface.
Flexif tx_flexif_clk[3:0]

rx_flexif_clk[3:0]

Per-port Flex I/F clocks.
alt_serdes tx_alt_serdes_clk[3:0]

rx_alt_serdes_clk[3:0]

Per-port Alternate low-frequency clock for the GT interface
For RX side:
  • Narrow mode, rx_serdes_clk[3:0] is used.
  • Wide mode rx_alt_serdes_clk[3:0] is used.
For TX side:
  • Narrow mode, tx_core_clk[3:0] is used.
  • Wide mode tx_alt_serdes_clk[3:0] is used.