Adjustment Interface - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

After a value has been established in the system_timer, it begins to increment by a fixed amount on a cycle-to-cycle basis. This fixed amount is labeled as timer_increment on the block diagram.

The amount of the increment can be adjusted in one of three methods. The desired method is selected using the signal ctl_tx/rx_ptp_st_adjust_type_N input. The update value is provided by ctl_tx/rx_ptp_st_adjust_N and the operation is triggered by toggling the value of ctl_tx/rx_ptp_st_adjust_vld_N.

Updates can be performed at any time, although changes should only be performed once every 10 clocks (system clocks) to avoid issues with retiming.

Method 1: Phase Adjustment (type = 2’b00)
The system_timer can be shifted in time by a specific amount (that is, a phase shift) using the system timer phase adjustment method. The provided adjustment is defined to be in units of 2-8 ns and is directly added to system_timer in addition to the usual timer increment. It is a one-time adjustment and you must repeat the operation again to add another amount. The maximum shift is (218 - 1) × 2-8 ns, or approximately 1 µs.
Method 2: Coarse Frequency Set (type = 2’b01)
In this mode, you can define a new increment value that is to be added to system_timer on a clock-by-clock basis. The provided increment value is interpreted as an unsigned integer in units of 2-8 ns. To make more fine-grained adjustments (< 2-8 ns) to increment_value, the next method must be used.
Method 3: Fine Frequency Adjust (type = 2’b10)
This method allows you to make sub-nanosecond adjustments to the interval value. The provided increment value is interpreted as a signed integer in units of 2-40 ns. It is added to the existing timer increment. This is a signed value, so subtraction is possible if a negative adjustment is provided.