AXI4-Lite Register Interface - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The MRMAC contains a soft logic 32-bit AXI4-Lite interface block to allow access to the integrated IP's APB3 interface. Through the AXI4-Lite interface, you can access the internal configuration, status, and statistics registers.

For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).

Table 1. AXI4-Lite Interface Signal Descriptions
Port Name I/O Description
s_axi_aclk I This clock is used for both the AXI4-Lite bridge Soft Logic and MRMAC APB3 port clock.
Note: The s_axi_aclk must be present for the MRMAC to function. If this clock is interrupted, the MRMAC enters an error state.
s_axi_areset I Active-High reset for the AXI4-Lite port. Asserting this reset alters the Port control logic and stops any in-flight writes/reads.

It does not reset the internal configuration registers with exceptions listed below.

s_axi_* I/O See the AXI to APB Bridge LogiCORE IP Product Guide (PG073) and the Vivado Design Suite: AXI Reference Guide (UG1037).
s_axi_pslverr O MRMAC AXI4-Lite slave error indication. This signal is Low during successful operation. When High, the signal indicates one of two issues has occurred:
  1. An AXI bus protocol error has occurred.
  2. There was a read/write attempt timeout failure during the transaction to the Port registers. This type of failure indicates that the MRMAC block could be in reset, or similar unrecoverable failure. The AXI4-Lite port and the MRMAC must be reset following such a failure.
Note: Writes or reads to non-existent/invalid register locations, nor a port being held in reset does not trigger a slave error indication. A set of debug signals stat_rsvd_out[179:178] are provided for diagnostics.
pm_tick[3:0] I Performance monitoring statistics tick signal.
pm_rdy[3:0] O Performance monitoring statistics counters ready flag. These per-port flags indicate that the internal statistics engine has completed a user-directed update cycle and are ready for access.

A complete description of the register map and the individual registers can be found in the Register Space section.

When the statistics engine is configured in extended mode by setting the ctl_counter_extend_<N> field of the per-port MODE_REG register to a 1, then the Statistics counter extension port is used to provide an increment for a set of external soft logic counters. The ext_count_addr bus cycles through all counters. When the internal 48-bit counter pointed to by the ext_count_addr address overflows, the increment signal ext_count_inc pulses to a 1.

Table 2. Statistics Counter Extension Signal Descriptions
Port Name I/O Description
ext_count_addr[8:0] O Indicates the address of the counter to increment with the value on the ext_count_inc bus.
ext_count_flags[3:0] O Indicates that a port has been issued a tick event at this point in the register rotation.
ext_count_inc O Increment value for the counter addressed by ext_count_addr bus