AXI4-Lite Clock and Reset - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The AXI4-Lite interface has its own clock and reset. The AXI4-Lite clock (s_axi_aclk) is independent of the remainder of the MRMAC clocks and can be any frequency to a maximum of 300 MHz.

Important: The AXI4-Lite clock must be present and stable for the MRMAC to operate. An interruption in the AXI4-Lite clock is likely to result in an unrecoverable internal MRMAC error. When the AXI4-Lite clock has returned and is stable, this requires a full reset-sequence to bring the MRMAC back to a stable condition.

Asserting the AXI4-Lite s_axi_areset pin results in:

  • A reset of the AXI4-Lite port and MRMAC APB3 control logic, stopping any in-flight writes/reads.
  • A reset of the current accumulated statistics and status registers for all slices. If only the AXI4-Lite port reset is asserted, then the internal statistics and status engines immediately begins monitoring the MRMAC operation and restarts the accumulations of the statistics counters.
  • A reset of all ports in User Scratch registers: USER_REG_0-3 to 0x0.
  • A reset of all ports in Reset registers: RESET_REG_0-3 to 0x0.

An AXI4-Lite reset does not reset the internal configuration registers.

In addition to the s_axi_aclk, the statistics and status registers require a port's core clock (rx_core_clk[N] and tx_core_clk[N]) be active and stable to operate. Unless the entire MRMAC is held in reset, all AXI4-Lite write/read transaction completes without asserting an s_axi_pslverr. If the s_axi_pslv_err is asserted, an event such as an unstable AXI4-Lite or core clock during a transaction has occurred, and the MRMAC must be reset.  If an RX statistics register read is required while the rx_serdes_clk[N]might be de-stabilized (that is, due to a GT RX reset), users can opt to clock the rx_core_clk[N] off of the tx_core_clk[N] domain.

If the AXI4-Lite port attempts a read or write access to the memory space of a disabled port (for example, ports with their clock tied to 0/1 or which are held in reset) or to a non-existent register address, the transaction completes and one of the debug signals stat_rsvd_out[179:178] toggle for one s_axi_aclk cycle. In such cases, the value on the AXI4-Lite port’s output is invalid.