XPLL - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2025-12-17
Version
1.1 English

Each IO Bank contains two XPLLs, one of which is required by the integrated DDRMC. If enabled, the DDRMC uses the left XPLL in the second bank of a triplet in all configurations. In addition, if DDRMC pins are assigned to other banks in that triplet, then the left XPLL for each used bank is also required.

For example, the first triplet of the VC1902 contain banks 700, 701, and 702.

  • XPLL_X0Y0 and XPLL_X1Y0 are in bank 700
  • XPLL_X2Y0 and XPLL_X3Y0 in bank 701
  • XPLL_X4Y0 and XPLL_X5Y0 in bank 702

Bank 701 is the second bank in the triplet, and XPLL_X2Y0 is the left XPLL in that IO bank. So XPLL_X2Y0 is used by the DDRMC regardless of the configuration, and XPLL_X0Y0 and XPLL_X4Y0 may be used if DDR pins are used in banks 700 and 702 respectively.

To monitor XPLL lock status, check the CMT_XPLL.REG_ISR.LOCK_B register. For more information, refer to REG_ISR (CMT_XPLL) Register in Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019).