Write leveling allows the controller to adjust each write DQS phase independently with respect to the CK forwarded to the DDR4/LPDDR4/4X SDRAM device. This compensates for the skew between DQS and CK and meets the tDQSS specification.
During write leveling, DQS is driven by the adaptive SoC memory interface and DQ
is driven by the DDR4/LPDDR4/4X SDRAM device to provide feedback. DQS is delayed until
the 0 to 1 edge transition on DQ is detected. The DQS delay is achieved using both
ODELAY and coarse tap delays.
After the edge transition is detected, the write leveling algorithm centers on
the noise region around the transition to maximize margin. This second step is completed
with only the use of ODELAY taps.