Write Latency Calibration is required to align DQS to the correct CK edge. During write leveling, DQS is aligned to the nearest rising edge of CK. However, this might not be the edge that captures the write command.
Depending on the interface type (UDIMM, RDIMM, LRDIMM, or component), the DQS could either be one CK cycle earlier than, two CK cycles earlier than, or aligned to the CK edge that captures the write command.
This is a pattern based calibration where coarse adjustments are made on
a per byte basis until the expected on time write pattern is read back. The process is
as follows:
- Issue extended writes followed by a single read.
- Check the pattern readback against the expected patterns.
- If necessary add coarse adjustments.
- Repeat until the on time write pattern is read back, signifying DQS is aligned to the correct CK cycle, or an incorrect pattern is received resulting in a Write Latency failure.