Vivado Hardware Manager – Memory Debug - Vivado Hardware Manager – Memory Debug - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

After programming, the AMD Vivado™ Hardware Manager displays all debug IP which includes integrated memory interfaces. This provides information such as memory IP configuration, status of calibration, calibration errors, and read/write window margin data. You can view this information in the GUI, or extract it to text files using Tcl.

Note: These properties are read back one time only, either upon completion of programming, or initial connection to an already programmed device. The properties do not update regularly. If the configuration changes after initial programming, you must refresh the device to re-download the latest properties. To do this, right-click on the device and select Refresh Device.