By default, the NoC compiler allocates the bandwidth of each NMU across all of its destinations. When accessing multiple destinations such as a memory controller, this division of bandwidth can lead to non-optimal routing to each destination. Multiphase constraints can be used to override this behavior and can be used for interleaved memory controllers, allowing potentially full bandwidth to each slave.
In the following example, two traffic generators are connected to the NoC in such a way as to allow each traffic generator (NMU) to access either of two memory controllers. Because the maximum bandwidth from an NMU is about 14 GB/s, each path can only be assigned a maximum of 7 GB/s.
The solution is to create a phase for each controller (phase 0 and phase 1 in this example) and enable multiphase mode only for NMUs that access multiple memory controllers.
Set one phase to the maximum desired bandwidth between all NMUs and one
controller, setting the bandwidth to 1 for the remaining controllers. Repeat this
process for each of the controllers. In the following figure, phase 0 assigns both NMUs
to have full bandwidth to the local MC Port 0 / MC Port 1. For phase 1, the full
bandwidth is assigned to M00_INI / M01_INI.
In this example it ensures that a topology is created that can provide full bandwidth to each MC, as shown in the following figure.