By default, the NoC compiler allocates the bandwidth of each NMU across all of its destinations. When accessing multiple destinations such as a memory controller, this division of bandwidth can lead to non-optimal routing to each destination. You can use multiphase constraints to override this behavior. These can be used for interleaved memory controllers, allowing potentially full bandwidth to each slave.
The following example uses two traffic generators connected to the NoC. They connect in such a way as to allow each traffic generator (NMU) to access either of two memory controllers. The maximum bandwidth from an NMU is about 14 GB/s. This means each path can only be assigned a maximum of 7 GB/s.
The solution is as follows:
- Create a phase for each controller (phase 0 and phase 1 in this example)
- Enable multiphase mode only for NMUs that access multiple memory controllers
Set one phase to the maximum desired bandwidth between all NMUs and one
controller, setting the bandwidth to 1 for the remaining controllers. Repeat this
process for each of the controllers. In the following figure, phase 0 assigns both NMUs
to have full bandwidth to the local MC Port 0 / MC Port 1. For phase 1, the full
bandwidth is assigned to M00_INI / M01_INI.
In this example, it ensures that the topology can provide full bandwidth to each MC, as shown in the following figure.