Transaction Size - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2024-11-13
Version
1.1 English
The choice of transaction size may affect performance. Comparing transaction sizes of 64, 128, and 256 bytes (1, 2, and 4 access quanta for a x64 DDR4 or x32 LPDDR4), the key things to consider are outstanding transactions (OT) and access locality.
  • For linear or random block access, transaction size does not directly impact performance but may indirectly impact it due to OT limitations. Therefore, longer transactions are preferred in these cases.
  • For random access, short transactions suffer the most DRAM access overhead, while longer transactions benefit from some locality and lower average overhead. Therefore, longer transactions will typically see higher efficiency.