Single Bit and Double Bit ECC Error Injection - 1.1 English

1. Unlock the NPI registers for the target pseudo channels of the controller. For example, write value 0xF9E8D7C6 to register REG_PCSR_LOCK of the HBMMC_NA0_12 register module to inject errors on pseudo channel 0 of HBM Controller HBM_MC_X0Y0. To inject errors on pseudo channel 1 of HBM_MC_X0Y0, write value 0xF9E8D7C6 to register REG_PCSR_LOCK of the HBMMC_NA1_12 register module.
2. Initialize the memory and then start the traffic.
3. Read REG_ISR of the target pseudo channels to ensure no error flags are set.
4. Read registers HBMMC_NA0_NA0_ERR_INJ and HBMMC_NA1_NA_ERR_INJ to ensure all bit fields are zero.
5. Inject a single bit error, write 0x8 to the error injection registers HBMMC_NA0_NA_ERR_INJ/HBMMC_NA1_NA_ERR_INJ based on the target pseudo channels. To inject a double bit error, write 0x10 to registers HBMMC_NA0_NA_ERR_INJ/HBMMC_NA1_NA_ERR_INJ.
6. Read error status register, REG_ISR for the target pseudo channel. If a single bit error was injected, bit 3 of this register should be set, indicating the single bit error was successfully injected and detected by the controller. If a double bit error was injected, bit 4 of this register should be set, indicating the double bit error was successfully injected and detected by the controller. A double bit error should result in SLVERR on the Read Response Channel of the AXI transaction.
7. Clear the error injection bit in the error injection registers HBMMC_NA0_NA_ERR_INJ/HBMMC_NA1_NA_ERR_INJ by writing 0x0.
8. Clear the error bit of error status register REG_ISR for the target pseudo channels. To clear the single bit error, write 0x8 to REG_ISR. To clear the double bit error, write 0x10 to REG_ISR.
9. Read error status register, REG_ISR for both pseudo channels to ensure it is set to 0.

For error injection Tcl command details, refer to AR 36295.