The Memory Controller uses a state machine to determine reordering priority. Depending on the state of the transactions, it either optimizes for efficiency (reordering to take advantage of open pages) or it services transactions which have been left idle for too long.
Generally, the memory controller reorders transactions to maximize page hits and to minimize bus turnarounds from reads to writes, and vice versa. Per-transaction timers are maintained for all outstanding transactions. If transactions have gone unserviced for too long, priority is shifted. Counters also monitor for starvation to ensure transactions are not stalled.
VC1902, VC1802, and VM1802 devices have a single read reordering buffer in each memory controller. When a memory controller is configured in dual-channel mode, half of the buffer is assigned to each channel. This reduced buffer depth results in efficiency loss for read operations because of the reduced reordering flexibility. The amount is dependent on the address pattern of the reads.
All other Versal devices have two read reordering buffers in each memory controller, yielding better read efficiency in both single- and dual-channel mode. See Versal Devices with Dual Read Reorder Buffers for more information.