These documents provide supplemental material useful with this product guide:
- 000034749 Versal ACAP DDRMC - How Do I Decode DDRMC ECC Errors?
- 000035076 Versal Adaptive SoC NoC - What are the NPI addresses associated with NoC/DDRMC sites?
- 75764 Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller - IP Release Notes and Known Issues
- ARM IHI 0051A
- Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019)
- Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)
- Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
- Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
- Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
- Versal Adaptive SoC Technical Reference Manual (AM011)
- Versal Adaptive SoC Register Reference (AM012)
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A)
- Versal Adaptive SoC PCB Design User Guide (UG863)
- Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
- Vivado Design Suite: AXI Reference Guide (UG1037)
- Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
- AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)
- Performance AXI Traffic Generator Product Guide (PG381)
- Programmable Network on Chip (NoC2) LogiCORE IP Product Guide (PG406)
- Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
- Versal Adaptive SoC Design Process Documentation
- Getting Started with Versal Memory Interfaces
- Memory and NoC Tutorials
- Obtaining and Verifying Versal Adaptive SoC Memory Pinouts