Random Addressing - Random Addressing - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

Recall that any system transaction larger than the DRAM’s basic access unit (typically 64 bytes) is chopped into individual DRAM commands. If addressing is random and transaction size is equal to the DRAM basic access unit, then no address mapping has an advantage. The DRAM controller reorders transactions to hide page access overhead as much as possible. Expected efficiency is around 40%.

Longer transactions create some short-term linear progression between commands and can benefit from mappings that are similar to the single-thread linear case. Below are results for 128-byte transactions.
Table 1. Random Traffic Address Mapping
Mapping Efficiency Mapping Type
16R-2B-1BG-7C-1BG-3C 78% Row-bank-column with bank group optimization
16R-2B-2BG-10C 63% Simple row-bank-column

The ‘Random Block’ addressing is a generalization of random addressing. When a random address is chosen, an entire block is read linearly. Using a badly fragmented virtual address system as an example. Linear access in the virtual domain can look like random block addressing in the physical domain, with block size equal to the address translation table.