The AMD Vivado™ tool suite supports two simulation models for the NoC: a SystemC transaction level model, (tlm), and a SystemVerilog register transfer model, (rtl). The tlm model is fast and efficient while the rtl model is near cycle-accurate (typically within 5% of hardware).
The NoC routing solution is
compiled from an aggregation of the traffic specifications of all of the NoC instances in the design. For this reason, a
single simulation model is constructed to represent the NoC as configured by the compiler. It is not possible to mix
rtl simulation for some NoC instances and
tlm for others. If there is a mismatch in simulation models, validate_bd_design issues an error.
You can select the simulation model by setting the SELECTED_SIM_MODEL property
on each of the axi_noc and axis_noc instances. The possible values of SELECTED_SIM_MODEL
are rtl (the default) and tlm. On the IP integrator canvas select each axi_noc instance and set the
SELECTED_SIM_MODEL property in the Block Properties menu. From Tcl issue the following
command.
set_property SELECTED_SIM_MODEL tlm [get_bd_cells /axi_noc_0]