QoS Tab - QoS Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document_ID
PG313
Release_Date
2026-06-23
Version
1.1 English

The following figure shows the Quality of Service (QoS) tab of the Customize IP dialog box. Use this tab to configure the QoS properties of every stream path defined in the axis_noc instance.

Figure 1. QoS Tab

The left column of the QoS tab shows a tree structure of the connectivity defined in the Connectivity tab. The top of each tree (left aligned port names) are the NoC ingress ports (S00_AXISin the figure). Shown under each ingress port are the associated rows for each connected egress port.

The second column defines the write traffic class. The possible values are ISOCHRONOUS and BEST_EFFORT (default). The traffic class applies to all connections originating from the given ingress port.

The third column indicates whether this NoC instance owns the QoS setting for a given path. A NoC path can go through multiple NoC instances using INI. The NoC instance that owns the QoS and path provides the QoS settings. QoS is ignored when a NoC instance does not own the path. Ownership is at the transition from an NMU or strategy=Driver to an NSU or strategy=Load.

A value of 'pending' means the ownership calculates during validate, or if you click Run NoC DRCs. For a value of 'error', validate or click Run NoC DRCs to view the error details in the Tcl Console and messages window.

The fourth column defines the Write Bandwidth expressed in MB/s or Gb/s. Allowed values range from 0, which blocks all write traffic, to the maximum data bandwidth of the NoC physical channel.

Select the QoS tab Advanced check box to expose additional columns that are described in QoS Tab.

Note: After validation the NoC QOS tab populates with read and write latency estimates. The Read Latency Estimate and Write Latency Estimate represent the round-trip structural latency through a portion of the NoC in the NoC clock domain. These numbers do not include latency in the DRAM, memory controller, PCB routing, and so on.

The actual total latency is greater than these numbers. These latency values are in NoC clock cycles. Use these values for relative comparison between different NoC implementations, not as a representation of the actual total latency.