You can also configure the integrated DDRMC as two independent DDR interfaces of 16 or 32 data bits each. This section describes the Flipped pin efficient 2x32 LPDDR4/4X interface.
Figure 1. Connections for a Pin Efficient 2x32 LPDDR4/4x Interface
The following figure shows the nibble utilization for a pin efficient 2x32
interface using two x32 components in the flipped configuration. DQ indicates data
nibbles. AC indicates Address/Command/Control nibbles. sys_clk indicates a nibble comprising the Reference Clock pair,
RESET_n, and ALERT_n signals. For a 1x32 interface all nibbles in the second Bank
and all nibbles except 8 in the first Bank are free.
Important: The
nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for Pin Efficient 2x32 Component Interface
(Flipped)
