LPDDR4 systems align write DQS with DQ during calibration, to account for mismatched receiver delay paths within the DRAM. This alignment must also be periodically adjusted to account for drift over time, and this requires periodic writes to memory. Hence, for LPDDR4 systems, the controller issues both periodic reads and periodic writes with an interval of 20 μs.
Memory access patterns with long continuous reads have a small efficiency impact because a write operation creates a read-write turnaround delay. If the memory access contains a mix of read and write commands, provided two writes are within 20 μs of each other, the controller does not need to insert any periodic writes.
Important: The simulation does not account for the
periodic writes or reads, regardless of whether the design is LP4DDR4 or DDR4. Hence,
there is a minor bandwidth mismatch between simulation and hardware.