The Versal Memory Controller periodically issues a read instruction to the DRAM to ensure that read clocks are returned for DQS gate tracking purposes. During calibration the DQS are aligned with an internal clock, and this alignment is adjusted during normal operation. This adjustment requires a read DQS. An internal counter keeps track of the time elapsed since a read DQS arrived. If one has not arrived in the last 20 μs, the controller inserts a 'dummy read' to receive the DQS for tracking. The data returned from the DRAM is discarded at the PHY and is not returned to the memory controller.
Memory access patterns with long continuous writes have a small efficiency impact because a read operation creates a read-write turnaround delay. If the memory access contains a mix of read and write commands, provided two reads are within 20 μs of each other, the controller does not need to insert any periodic reads.