PHY BISC - PHY BISC - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document_ID
PG313
Release_Date
2026-06-23
Version
1.1 English

This calibration stage measures internal delays to determine the number of fine taps required to equal a quarter clock memory period. This is referred to as a coarse tap.

Table 1. PHY BISC Calibration Register
Register Name Quantity Description
Fx_CALBISC_RL_DLY_QTR 1 Number of fine taps to equal ¼ memory clock period.