Outputs Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2025-05-29
Version
1.1 English

The Outputs tab of the Customize IP dialog box is shown in the following figure and allows the configuration of the output ports.

Figure 1. Outputs Tab

AXI Outputs
Set the number of AXI outputs from this instance and configure each output. The configuration options are:
Connected To
PL
To the programmable logic fabric.
AIE
To the AI Engine array.
PS Cache Coherent Virtual
To one of the cache coherent interfaces on the PS. All PL masters that route to this NSU port use Fixed DestID addressing to route all transactions from the NMU to the NSU. This setting is for endpoint masters that use features in the SMMU-400 and/or the CCI-500.
PS Cache Coherent Physical
To one of the cache coherent interfaces of the PS. All PL masters that route to this NSU port use Address decode addressing to route transactions. This setting is for endpoint masters that target endpoint slaves in the PS. It is not for endpoint masters that use features in the CCI-500.
PS Non-Coherent Virtual
To one of the non-coherent interfaces on the PS. All PL masters that route to this NSU port use Fixed DestID addressing to route all transactions from the NMU to the NSU. This is for endpoint masters that use features in the SMMU-400.
PS Non-Coherent Physical
To one of the non-coherent interfaces of the PS. All PL masters that route to this NSU port use Address decode addressing to route transactions. This setting is for endpoint masters that target endpoint slaves in the PS.
PS PCIe
To the PCIe interface of the PS.
PS PMC
To the Platform Management Controller of the PS.
Parity
Enables parity checking of the connection from the NSU to the AXI slave, even parity is used.
The parity options are the same as those described for the Inputs tab. Mapping of the parity bits is described in the following table.
Table 1. NSU Parity Pin Mapping
NSU Pin Direction Width AXI Signal
AXI AWADDR Parity OUT 8 AWUSER[17:10]
AXI ARADDR Parity OUT 8 ARUSER[17:10]
AXI WDATA Parity OUT 64 WUSER[127],WUSER[125],WUSER[123],…,WUSER[3],WUSER[1]
AXI RDATA Parity IN 64 RUSER[127],RUSER[125],RUSER[123],…,RUSER[3],RUSER[1]
AXI WPOISON OUT 1 WUSER[0]
AXI RPOISON IN 1 RUSER[0]
Note: Parity checking is only available for outputs connected to PL. No parity checking is available to PS or AI Engine.
Inter-NoC Outputs
Specify outputs to other axi_noc instances using the Inter-NoC Interface (INI).
You might optionally set the INI Connection Strategy as follows:
Auto
Allows IP integrator to determine the correct strategy. This is the default.
Single Driver (NMU). Load (NSU/MC) owns PR path and has QoS.
Has a single driver and possibly multiple loads.
Single Load (NSU/MC). Driver (NMU) owns PR path and has QoS.
Has a single load and possibly multiple drivers.