The first step in the planning process is to provide accurate bandwidth estimates to the NoC compiler. These estimates help the compiler allocate resources appropriately and avoid over- or under-provisioning. Without realistic bandwidth numbers, the NoC can either become a bottleneck or waste valuable routing and buffering resources. Therefore, understanding the expected traffic patterns is essential to achieving optimal performance and avoiding costly redesigns.
A paper-based analysis of your system is the essential first step in mapping it to the NoC. For example, in an ADAS design, understanding the high-level data flow through the device helps establish a foundation for traffic planning.
The next step is to map traffic patterns and estimate bandwidth. For well-defined data paths—such as video streams—bandwidth calculations are straightforward. However, when the data volume between IP blocks is unknown, a worst-case estimate can be used by multiplying the AXI bus width by its operating frequency. This conservative approach provides a safe starting point and can be refined later as more accurate data becomes available.
After the traffic block diagram is complete, you can map the design onto the NoC. To validate that the NoC can meet system requirements before the full design is mapped, AMD provides Performance Traffic Generator IP and ways to measure bandwidth and latency. These tools simulate traffic patterns and are supported by extensive tutorials available on AMD's GitHub Repository.
With this information priorities might need to be set. One critical aspect of Versal architecture is that access to the DDR and HBM Memory Controller are exclusively routed through the NoC. This means that any design intending to use DDR memory must first establish a reliable and prioritized path through the NoC. Without this, memory access might be bottlenecked. Therefore NoC planning is a foundational step in system integration.
In cases where AXI4-Lite interfaces are required for low-bandwidth, control-type transactions it can be beneficial to use the NoC routing rather than utilizing fabric resources for this purpose. Doing so allows for simpler integration and can save fabric resources, especially when the AXI4-Lite interface is used for one-time setup or configuration tasks. To do so, connect the AXI bus master to a slave interface port on the NoC and enable connectivity to destination master ports. Because the NoC IP does not natively support AXI4-Lite, a SmartConnect IP needs to be instantiated and connected between the NoC master port and the peripheral(s) to provide the bridging function.
Before full design mapping, use AMD traffic generators (see Performance AXI Traffic Generator Product Guide (PG381)) and measurement tools (NoC AXI Performance Monitor IP) to validate NoC performance. Because DDR and HBM memory access must route through the NoC, prioritizing these paths is critical. After securing memory access, evaluate AXI4-Stream and AXI4-Lite interfaces, and convert AXI4-Lite to AXI4 when beneficial for integration and resource savings.
NoC planning requires a balancing of prioritization of memory access, assessing stream requirements, and optimizing control paths, while ensuring system-wide efficiency and scalability. The next sections explain how to apply these strategies.