The interleave feature of the NoC compiler simplifies system-level memory architecture by presenting multiple memory controllers—such as DDRMCs—as a unified address space. This abstraction enables software and hardware designers to treat several physical memory interfaces as a single logical memory region.
At the hardware level, the NoC achieves this by mapping specific address bits to different DDRMCs. As addresses increment, the routing logic automatically transitions between controllers, allowing seamless access across the unified memory space. The interleave size determines the granularity of memory striping assigned to each of the controllers.
In a two-DDRMC configuration, the compiler assumes an alternating access pattern, distributing memory traffic evenly—an average 50% bandwidth to each DDRMC. For example, if a single NMU is configured to interleave between two DDRMCs with a QoS setting of 10 GB/s, the NoC compiler allocates 5 GB/s to each DDRMC.