The NoC Compiler is designed to automate and optimize the configuration of the NoC interconnect fabric within Versal adaptive SoC designs. Its primary intention is to translate a user-defined traffic specification—comprising connectivity, bandwidth, and quality-of-service (QoS) requirements—into a hardware-valid NoC configuration that guarantees dead lock avoidance and meets performance goals, while respecting architectural constraints.
What the NoC Compiler is
- A structural optimizer
- The compiler determines routing paths, allocates bandwidth, and assigns traffic classes to ensure that latency and throughput requirements are met.
- A constraint solver
- The compiler interprets user-defined QoS and bandwidth constraints and attempts to find a feasible solution that satisfies all requirements.
- A validation tool
- The compiler checks for violations such as oversubscription, unsupported routing configurations, and incompatible traffic classes.
- A hardware-aware compiler
- The compiler understands the physical layout and capabilities of the NoC fabric and generates configurations that are implementable in silicon.
What the NoC Compiler is Not
- A dynamic traffic manager
- The compiler does not enforce runtime traffic shaping or rate limiting. If a master port exceeds its specified bandwidth, it can degrade the performance of other connections, especially those marked as 'Best Effort'.
- A performance predictor
- While it aims to meet QoS targets, the compiler does not simulate actual traffic behavior or guarantee real-world performance under all conditions.
- A debugging tool
- The compiler does not provide runtime diagnostics or error tracing. These functions are handled by performance monitors and error registers accessible via ChipScoPy or the NPI bus.