Multi-Thread Linear Read/Write - Multi-Thread Linear Read/Write - 1.1 English - PG313

This example uses two read devices and two write devices, all operating concurrently, and each linearly accessing a different memory region. Similar to the previous example, it is beneficial for each device to open a page and access it linearly without page miss interruptions. To achieve this, ‘place’ each device in a separate bank, while keeping one bank group bit in the low order bits as before to avoid same-group penalty.

To achieve this, decide how to partition the memory between the four devices. For example, allocate 32 MB for each device. To ensure that each device is accessing a different bank, place the bank bits at the position corresponding to 32 MB boundary: 6R-2B-1BG-11R-7C-1BG-3C.

This approach works well with up to eight devices because each device occupies two banks. With more than eight devices, expect some performance degradation.