Monitoring ECC Status - 1.1 English - PG313

Status Registers to Find Correctable and Uncorrectable Errors

In HW manager, under DDRMC* ecc, the following status registers can be observed:

• DDRMC_ISR_CE0_ECC0
• DDRMC_ISR_CE0_ECC1
• DDRMC_ISR_CE1_ECC0
• DDRMC_ISR_CE1_ECC1
• DDRMC_ISR_UC0_ECC0
• DDRMC_ISR_UC0_ECC1
• DDRMC_ISR_UC1_ECC0
• DDRMC_ISR_UC1_ECC1

• In the above status registers, the first 0 or 1 (CE* and UC*) indicates which half of the BLn burst contained an error, and the last 0 or 1 (ECC*) indicates the DDRMC channel number containing an error.
• When one or more errors are injected, HW will set the reg_adec15.done bit to 0x1 under DDRMC_NOC* registers.
• In persistent mode, errors will continue to be injected after the done bit is set.
• In single mode (persistent=0x0) the done bit must be cleared to enable another single error injection.
• During correctable error detection DRAM will be scrubbed.
• During uncorrectable error detection SLVERR Read response will be returned to the host.

Decoding DDRMC ECC Errors

ECC error checking is done on every edge of the memory burst, either BL8 for DDR4, or BL16 for LPDDR4. ECC error reporting is done on an aligned two burst boundary for x72 DDR4 and an aligned four burst boundary for all other memory configurations. The eccr[1:0]_corr/uncorr_err_status registers indicate the memory bursts associated with the ECC errors. This burst mapping also depends on the memory technology and interface width. The following tables show the correctable and uncorrectable burst mapping possibilities.

For information refer to AR 000034749.