Memory Controller Interleaving - Memory Controller Interleaving - 1.1 English - PG313

The NMU supports interleaving memory transactions across two or four hardened memory controllers. The memory regions can be programmed to be interleaved at a granularity of 128 bytes to 4 KBytes, or can be programmed to disable interleaving. You determine whether to interleave, the interleave granularity, and the address of the interleaved region when configuring the NoC. The interleave granularity must match the stripe size of the CCI-500 if the PS full power domain is enabled. The default stripe size for the CCI-500 is 4 kB.

If you enable interleaved memory controllers, the NMU stripes transactions bound for the DDR across the two or four memory controllers as follows:

1. The NMU chops the transaction into smaller packets to align with the memory space of each physical channel. Packet chopping occurs on the interleave boundary between each memory channel.
2. Each sub-packet is addressed separately to the correct physical DDR controller.
3. Responses are re-assembled at the NMU and returned to the attached master.