Latency changes can occur depending on the location of the NMU site in relation to the NSU. Increased distance typically results in increased NoC component usage. This leads to an increase in latency and, in turn, a decrease in read/write bandwidth. Furthermore, in multi-SLR (SSI technology) devices, the change in latency is more significant when passing between SLRs.
The following figure shows an example of this change in latency and read bandwidth. The example shows a plot of read bandwidth and latency for a single traffic generator connecting to an LPDDR4 interface through a DDRMC from various NMU sites across the leftmost VNoC (X-coordinate 0) of a multi-SLR (SSI technology) device. The trend shows a linear decrease in read bandwidth as the NMU site Y-coordinate increases. This corresponds to the NMU location getting further from the DDRMC. Significant drops in read bandwidth occur between SLR crossings (NMU site Y-coordinates 6 to 7, 12 to 13, and 18 to 19).
This change in latency and read bandwidth is due to the following:
- Signals being routed through NPS blocks along the VNoC and HNoC.
- NIDB blocks connecting the VNoC between SLRs in multi-SLR (SSI technology) devices (refer to Figure 2).
Differences in latency and bandwidth between VNoCs within the same SLR while keeping the DDRMC site static are consistent with routing through additional NPS blocks along the HNoC. This behavior is inherent to Versal devices and you need to account for it when designing to maximize NoC performance.