LRDIMM MWD Cycle Training - LRDIMM MWD Cycle Training - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

This training finds the correct cycle to maintain the set Write Latency value in the DRAM. In this training mode, the following occurs:

  • The controller pre-programs the data buffer MPR registers with the expected pattern
  • The controller issues write commands to load the data into memory
  • Thh controller issues reads to the memory

The data buffer compares the read data with the expected data and feeds back the result on to the DQ bus. Calibration identifies the correct cycle based on the result of the comparison.

Table 1. MWD Cycle Training Register
Register Name Quantity Description
Fx_DB_DWL_MWD_LAT Rank Data Buffer to DRAM latency [8:6] and Data Buffer phase [5:0]