Memory Configuration Support in the DDR Memory Controller section of this Product Guide lists the supported configurations for LPDDR4/4X.
Recommended: Try the Obtaining and Verifying Versal Adaptive SoC Memory Pinouts
tutorial available on GitHub. This is a fast
and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be
captured in the design's XDC and validated before generating hardware. PCB level pin
swaps not captured in the tools can lead to hardware failures if pin rules are not
followed.
Important: LPDDR4/4X protocol uses
feedback on the DQ bits during CA Training and Write Leveling calibration stages so any
pin swapping needs to be done and validated in the tools. Additionally the DQ mapping
from the adaptive SoC to the LPDDR4/4X component channels needs to maintain an exact 1:1
mapping. For example, LPDDR4_DQ_A[0] must be connected to DQ0 of Channel A of the LPDDR4
component. It follows LPDDR4_DQ_A[1] is connected to DQ1 of Channel A, through
LPDDR4_DQ_B[15] is connected to DQ15 of Channel B of the LPDDR4 component.