LPDDR4 Refresh Options - LPDDR4 Refresh Options - 1.1 English

LPDDR4 Refresh Options - LPDDR4 Refresh Options - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2026-06-23

Version

1.1 English

The DDRMC supports the following two DRAM refresh options for LPDDR4:

All-bank refresh
Per-bank Refresh

For all-bank refresh, all banks must be precharged before a refresh is issued. This means all banks are unavailable for the duration of the refresh operation (tRFC, e.g., 280 ns for 4267 speed). All-bank refresh makes the entire DRAM unavailable for about 7% of the time.

For per-bank refresh, each bank is issued a separate refresh command. This means while one bank is refreshed, the other banks are available. The duration of the per-bank refresh is shorter (tRFCpb, e.g., 140 ns for 4267 speed). Per-bank refresh makes each bank unavailable for about 3.5% of the time.

Using per-bank refresh can reduce and even eliminate the performance loss due to refresh. However, results heavily depend on traffic pattern and address mapping, and can in some cases be worse than all-bank refresh.