Internal System Clock - 1.1 English - PG313

The DDRMC internal clock uses the HSM1 reference clock generated from the CIPS and is routed to the hardened DDRMCs. Using the internal clock removes the need for an external clock generator and biasing circuit, while also saving PCB space and reducing power.

The HSM1 clock is common across all of the enabled DDRMCs in a design, so all DDRMCs must be set to the same internal System Clock frequency. The DDRMCs have a minimum supported system clock frequency of 100 MHz, and the maximum HSM1 clock frequency is 200 MHz. Therefore the supported HSM1 frequency operating range for the DDRMCs is 100 MHz to 200 MHz.

Using the HSM1 reference clock does not reduce the maximum supported operating rates for the DDRMC interfaces or have any negative impacts on DDRMC performance.

Following are the steps to enable and use the HSM1 internal clocking for the DDRMC.

The minimum design must have a CIPS block and a NoC with a DDRMC enabled. The following figure shows an example of a simple design from block automation.

1. Open the AXI NoC and go to the DDR Basic tab.
   
   
2. Change the Clock selection from Memory Clock to System Clock.
   
   

   Changing the Clock selection to System Clock simplifies the process of selecting reference clock frequencies and interface operating rates because most data rates can be achieved by 133 MHz (7500 ps) or 200 MHz (5000 ps) reference clocks.

3. Set the Input System Clock period to 5000 ps for 200 MHz and set the System Clock option to Internal.
   
   

   It is also recommended to check the box for Enable Internal Responder when running DDRMC traffic simulations.

4. Click OK. The configuration GUI closes.
5. If an external sys_clk port exists on the IP integrator canvas from automation, it is now safe to delete it from the design.
6. Double click the CIPS block to open the configuration GUI:
   1. Navigate to the PS PMC tab and then select the PSPMC tab for SLR0.
   2. Click the Clocking tab and select SLR0.
   3. Select the Output Clocks tab, expand the PMC Domain Clocks, and expand the Processor/Memory Clocks.
   4. Enable the HSM1 clock if it is not already checked, and set the Requested Freq (MHz) to 200 MHz to match the DDRMC expectations.
      
      
7. Select the NoC tab and check the box to enable the DDRMC HSM1 Clock Port in the PS to NoC Clocks section.
   
   
8. Click OK to close the GUI and then click Finish to exit.
9. Connect the hsm1_ref_clk port from the CIPS to the sys_clk0 port of the DDRMC.