Incremental Design Flow for NoC Compiler - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2025-12-17
Version
1.1 English

It is possible to compile a NoC solution for a subsystem of the design, lock the NoC solution, and then import that subsystem along with its NoC solution into the design.

Using this flow requires the subsystem to be synthesized and the NoC routes locked prior to writing out a DCP. You can then import the DCP into the design using read_checkpoint and the locked NoC paths are imported with the subsystem.