The HBM_NMU available on Versal HBM Series connects the PL fabric array to the HBM controllers via a set of low latency NoC paths. The addition of these localized HBM_NMUs is necessary to fully use the HBM bandwidth by providing direct access from PL to the HBM. The HBM_NMUs are distributed evenly across the PL for ease of timing closure.
The AXI data width of the HBM_NMU is configurable from 32 bits to 256 bits. The HBM_NMU does not support the AXI4-Stream protocol. The Read Reorder buffer is larger than other NMUs with 64 entries of 64 bytes per entry instead of 32 bytes per entry. The HBM_NMUs support three different Write Ordering schemes.
Set AxCache[1] to mark AXI transactions as modifiable when they meet these conditions:
- AxSize < 4
- AxLen > 0
- Originate in the fabric, and target HBM memory