ECC - ECC - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

Error Correction (Single Error Correct, Double Error Detect) performs checks of read data without interrupting traffic. An additional byte stores the ECC requirements, regardless of the data width. For example, a 64-bit DRAM interface with ECC enabled needs an additional byte, making the entire interface 72 bits. Similarly, a 32-bit interface with ECC enabled also needs an additional byte, making the entire interface 40 bits.

For each burst single-bit errors are correctable. Double-bit errors are detectable but uncorrectable. ECC might or might not detect three or more bit errors. these are not correctable.

If ECC detects errors, correctable or uncorrectable, they are logged and can be configured to generate an interrupt. Correctable and uncorrectable errors can be injected on write operations.

Note: ECC adds two memory clock cycles of latency during writes when the CAS Write Latency is less than 11.