The HBM controller supports single-bit and dual-bit error injection on system write data per pseudo channel. Before starting ECC error injection, make sure that memory has been initialized. Once the memory is initialized, the traffic can be sent to the controller. ECC errors can be injected on system write data by configuring associated write data error injection registers. The following HBM NPI module registers are required for error injection and monitoring error status.
- Module HBMMC_NAx_y
- where x = 0, or 1 indicates the pseudo channel per HBM controller
- where y = 0 to 15 indicates the HBM controller, a total of 16 controllers with two stacks. The mapping of the physical controller to the y index is listed in Table 1.
- For example, HBMMC_NA0_12 is associated with pseudo channel 0 of the physical controller HBM_MC_X0Y0.
- The relevant registers within the module HBMMC_NAx_y are:
| Register Name | Bits | Description |
|---|---|---|
| REG_PCSR_LOCK | Bit 0 |
‘1’ indicates the Register module is locked. ‘0’ indicates the Register module is unlocked. |
| REG_ISR | Bit 3 | Flags single bit error on Read data from HBM memory |
| Bit 4 | Flags double bit error on Read data from HBM memory and SLVERR sent to NoC. | |
| HBMMC_NAx_NA_ERR_INJ | Bit 3 | ‘1’ setting injects Single bit correctable error at the next write command for pseudo channel x. Error detected when data is read. |
| Bit 4 | ‘1’ injects Double bit uncorrectable error at the next write command for pseudo channel x. Error detected when data is read. |