The HBM controller supports single-bit and dual-bit error injection on system write data per pseudo channel. Ensure that memory is initialized before starting ECC error injection. The traffic can be sent to the controller after the memory is initialized. You can inject ECC errors on system write data by configuring data error injection registers. Error injection and monitoring error status requires the following HBM NPI module registers:
- Module HBMMC_NAx_y
- where x = 0, or 1 indicates the pseudo channel per HBM controller
- where y = 0 to 15 indicates the HBM controller, a total of 16 controllers with two stacks. Table 1 lists the mapping of the physical controller to the y index.
- For example, HBMMC_NA0_12 is associated with pseudo channel 0 of the physical controller HBM_MC_X0Y0.
- The relevant registers within the module HBMMC_NAx_y are as follows:
| Register Name | Bits | Description |
|---|---|---|
| REG_PCSR_LOCK | Bit 0 |
‘1’ indicates the Register module is locked. ‘0’ indicates the Register module is unlocked. |
| REG_ISR | Bit 3 | Flags single bit error on Read data from HBM. |
| Bit 4 | Flags double bit error on Read data from HBM and SLVERR sent to NoC. | |
| HBMMC_NAx_NA_ERR_INJ | Bit 3 | ‘1’ setting injects Single bit correctable error at the next write command for pseudo channel x. Error detected when data is read. |
| Bit 4 | ‘1’ injects Double bit uncorrectable error at the next write command for pseudo channel x. Error detected when data is read. |