The AMD Versal™ adaptive SoC tool flow introduces a pair of IP cores, the AXI NoC and the AXI4-Stream NoC (AXIS NoC). These IP cores act as logical representations of the Versal programmable NoC. The axi_noc supports the memory mapped AXI protocol while the axis_noc supports the AXI4-Stream protocol. A Versal platform design can include multiple instances of each of these IP cores. Each instance specifies one or more connections to be mapped onto the physical NoC, along with the quality of service requirements for each connection. IP integrator automatically aggregates the connectivity and quality of service information from all of the logical NoC instances to form a unified traffic specification. This traffic specification computes an optimal configuration for the NoC.
The axi_noc IP core integrates the integrated memory controllers (MCs). You can configure an instance of the axi_noc to include one, two, or four instances of the integrated MC. If you select two or four instances of the MC, they form a single interleaved memory. Each non-interleaved memory controller requires a separate axi_noc instance.
For guidance on the NoC/DDRMC design flow, refer to the NoC Design Flow Tutorials.