DRAM Power Down - DRAM Power Down - 1.1 English

DRAM Power Down - DRAM Power Down - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2026-06-23

Version

1.1 English

The Versal Memory Controller supports activity-based DRAM Power Down. When the Memory Controller is idle for a programmable amount of clock cycles, it drives the DRAM CKE low to enter power down mode. The DRAM is periodically taken out of power down mode as required for refresh operations or for ECC scrubbing. The DRAM is taken out of power down mode automatically when memory transactions are received. This adds a delay of about 50 memory clock cycles.