DRAM address mapping is the way the system physical address (for example a 32-bit byte address delivered via AMBA AXI bus) maps to the physical DRAM address bits. Physical DRAM address bits are partitioned into rows, columns, banks, and bank groups, and so on. The address mapping is usually programmable in the DRAM controller and is selected at initialization time. There is no 'one-size-fits-all’ mapping. Different mappings maximize performance of different workloads or traffic patterns.
Factors affecting choice of mapping include the following:
- Address progression: linear, random, rectangular, and so on.
- Transaction size (64, 128, 256 bytes, and so on.)
- Number of threads (that is, the number of individual devices accessing memory)
- Multi-thread memory space partitioning
Note: It is possible to pick a default address mapping that is a
‘middle-of-the-road’ solution which provides
reasonable performance. But for specific use cases that have well-defined traffic
patterns and demand for the highest possible performance, the correct choice is
crucial.