During this stage of calibration, the read DQS preamble is detected and the gate
to enable data capture within the adaptive SoC is calibrated to be one clock cycle
before the first valid data on DQ. The coarse and fine DQS gate taps (RL_DLY_COARSE and RL_DLY_FINE) are adjusted during this stage. Read commands are issued with
gaps in between to continually search for the DQS preamble position. The DDR4/LPDDR4/4X
preamble training mode is enabled during this stage to increase the low preamble period
and aid in detection. During this stage of calibration, only the read DQS signals are
monitored and not the read DQ signals. DQS Preamble Detection is performed in parallel
for all bytes. During this stage of calibration, the coarse taps are first adjusted
while searching for the low preamble position and the first rising DQS edge.
If the preamble is not found, the read latency is increased by one. The coarse taps are reset and then adjusted again while searching for the low preamble and first rising DQS edge. After the preamble position is properly detected, the fine taps are then adjusted to fine tune and edge align the position of the sample clock with the DQS.