DDRMC Calibration Debug - DDRMC Calibration Debug - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

You can obtain all references to register names in the following sections from the Vivado Hardware Manager Properties window and Properties tab. Alternatively, use the Tcl command described in the previous section.

The register names provided in this section can be matched to register names in the Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019). This document provides the NPI address values for each register, enabling you to implement your own method to check the calibration status. In this document, there are two sections, DDRMC_DDR4_XRAM Module and DDRMC_LPDDR4_XRAM Module. Select the appropriate module based on the target memory interface type, as the register contents and locations vary.