DDR4 UDIMM and SODIMM Interfaces - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-11-13
Version
1.1 English

PCB Expansion Options:

  • Optimum
  • Rank Expansion

The Versal DDR4 controller supports single slot DDR4 UDIMM and SODIMM topologies which can be single rank or dual rank. From a pinout and memory topology perspective the DDR4 UDIMM and SODIMM implementations are identical and will be referred to as UDIMM/SODIMM since there is no difference aside from the physical slot and form factor. UDIMM/SODIMM pinouts differ from component interfaces in the CAC bus signals placement in the Center Bank for easier routing to the connector. For UDIMM/SODIMM topologies there are two distinct pin maps. The first is Optimum which only supports single rank devices and leaves three free Nibbles open in the Right bank. The second is Rank Expansion which supports both single rank and dual rank UDIMM/SODIMM devices. If there is a need for increased memory capacity in the future then the Rank Expansion option must be selected, otherwise, if only single rank devices will be used then this can be left at Optimum. If the UDIMM/SODIMM configuration is dual rank then the only pinout option will be Optimum which is the Rank Expansion pinout. UDIMM/SODIMM standards do not support 3DS devices. Note that for a 64-bit, Single Rank UDIMM/SODIMM interface without ECC, nibbles 4 and 5 in addition to nibbles 6, 7, and 8 in the third Bank would be free. For a 64-bit Multi-rank (Single Slot, 2 Rank) UDIMM/SODIMM interface without ECC, nibbles 0 and 1 in addition to nibble 8 in the third bank would be free.

Figure 1. Single Rank DDR4 UDIMM/SODIMM 64-bit or 72-bit Pinout
Figure 2. Rank Expansion Single or Dual Rank DDR4 UDIMM/SODIMM 64-bit or 72-bit Pinout