DDR4 Pinout for UDIMM/SODIMM Interfaces (Non-Flipped) - DDR4 Pinout for UDIMM/SODIMM Interfaces (Non-Flipped) - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document_ID
PG313
Release_Date
2026-06-23
Version
1.1 English

The following figure shows the nibble utilization for a 72-bit, Single Rank UDIMM/SODIMM interface with ECC in the non-flipped configuration. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n. Note that for a 64-bit, Single Rank UDIMM/SODIMM interface without ECC, nibbles 4 and 5 in addition to nibbles 6, 7, and 8 in the third Bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble Utilization for 72-bit Single Rank UDIMM/SODIMM with ECC (Non-flipped)

The following figure shows nibble utilization for a 72-bit, Multi-rank (Single Slot, 2 Rank) UDIMM/SODIMM interface with ECC in the non-flipped configuration. Note that for a 64-bit Multi-rank (Single Slot, 2 Rank) UDIMM/SODIMM interface without ECC nibbles 0, and 1 in addition to nibble 8 in the third bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 72-bit Multi-Rank (single slot, 2 rank) UDIMM/SODIMM with ECC (Non-flipped)