DDR4 Pinout for Component Interfaces (Non-Flipped) - DDR4 Pinout for Component Interfaces (Non-Flipped) - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

The following figure shows the nibble utilization for a 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 1CK pair in the non-flipped configuration. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a reduced data width of 64-bits, nibbles 4 and 5 in addition to nibbles 6, 7, and 8 in the third Bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble Utilization for 72-bit Interface using x8, x16, x8 DDP 2 Rank, or 3DS Components with 1CK (Non-Flipped) X29262 Process.73 First Bank First Bank Process.74 Second Bank Second Bank Process.75 Third Bank Third Bank Process.76 0 0 Process.77 1 1 Process.78 2 2 Process.79 3 3 Process.80 8 8 Process.81 4 4 Process.82 5 5 Process.83 6 6 Process.84 7 7 Process.85 0 0 Process.86 1 1 Process.87 2 2 Process.88 3 3 Process.89 8 8 Process.90 4 4 Process.91 5 5 Process.92 6 6 Process.93 7 7 Process.94 0 0 Process.95 1 1 Process.96 2 2 Process.97 3 3 Process.98 8 8 Process.99 4 4 Process.100 5 5 Process.101 6 6 Process.102 7 7 Process.104 sys_clk sys_clk Process.105 AC AC Process.106 AC AC Process.107 AC AC Process.108 AC AC Process.109 DQ DQ Process.110 DQ DQ Process.111 DQ DQ Process.112 DQ DQ Process.113 DQ DQ Process.114 DQ DQ Process.115 DQ DQ Process.116 DQ DQ Process.117 DQ DQ Process.118 DQ DQ Process.119 DQ DQ Process.120 DQ DQ Process.121 Process.122 Sheet.50 Nibble # Nibble # Sheet.51 Signals Signals Sheet.52 Sheet.53 Process.128 DQ DQ Process.129 DQ DQ Process.130 AC AC Process.131 Free Free Sheet.58 Fixed (64-bit) Fixed (64-bit) Sheet.59 Fixed (64-bit) Fixed (64-bit) Process.134 Process.135 Process.136 Free Free Process.137 Free Free Sheet.64 Free (64-bit) Free (64-bit) Sheet.65 Free (64-bit) Free (64-bit) Process.140 DQ DQ Process.141 DQ DQ Sheet.68 X29262-040324 X29262-040324
Note: You can use free pins in a DQ nibble as Address/Command/Control pins.

The following figure shows the nibble utilization for a 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 2CK pairs in the non-flipped configuration. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a reduced data width of 64-bits, nibbles 6, and 7 in addition to nibble 8 in the third Bank and nibble 2 in the first Bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 72-bit Interface using x8, x16, x8 DDP 2 Rank, or 3DS Components with 2CK (Non-Flipped) X29266-Nibble utilization for 72-bit interface using x8x16 DDP (2 rank) or 3DS Process.507 First Bank First Bank Process.2 Second Bank Second Bank Process.3 Third Bank Third Bank Process.4 0 0 Process.5 1 1 Process.6 2 2 Process.7 3 3 Process.8 8 8 Process.9 4 4 Process.10 5 5 Process.11 6 6 Process.12 7 7 Process.13 0 0 Process.14 1 1 Process.15 2 2 Process.16 3 3 Process.17 8 8 Process.18 4 4 Process.19 5 5 Process.20 6 6 Process.21 7 7 Process.22 0 0 Process.23 1 1 Process.24 2 2 Process.25 3 3 Process.26 8 8 Process.27 4 4 Process.28 5 5 Process.29 6 6 Process.30 7 7 Process.32 AC AC Process.33 sys_clk sys_clk Process.34 AC AC Process.35 AC AC Process.36 AC AC Process.37 AC AC Process.38 DQ DQ Process.39 DQ DQ Process.40 DQ DQ Process.41 DQ DQ Process.42 DQ DQ Process.43 DQ DQ Process.44 DQ DQ Process.45 DQ DQ Process.46 DQ DQ Process.47 DQ DQ Process.48 DQ DQ Process.49 DQ DQ Process.50 DQ DQ Process.51 DQ DQ Process.52 Process.57 Sheet.54 Nibble # Nibble # Sheet.55 Signals Signals Sheet.56 Sheet.57 Process.58 Free Free Process.59 DQ DQ Process.60 DQ DQ Process.64 AC AC Process.65 Free Free Process.507.65 Process.66 Sheet.68 Free (64-bit) Free (64-bit) Sheet.70 Free (64-bit) Free (64-bit) Sheet.71 X29266-040424 X29266-040424

The following figure shows the nibble utilization for a 40-bit interface using x4 DDP (2 Ranks) or 3DS components with 2CK pairs in the non-flipped configuration. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 3. Nibble Utilization for 40-bit Interface using x4 DDP (2 Rank) or 3DS Components with 2CK (Non-Flipped)