DDR4 Pinout for 2x Component Interfaces (Flipped) - DDR4 Pinout for 2x Component Interfaces (Flipped) - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

You can also configure the DDRMC as two independent DDR interfaces of 16, 24, or 32 data bits each. This section includes the flipped 2x component pinout configurations.

The following figure shows the nibble utilization for a 2x32 interface using SDP, DDP (2 Ranks) or 3DS components in the flipped configuration. DQL and DQR indicate data nibbles for the left and right interfaces respectively. ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively. sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x32 interface all nibbles in the second Bank and nibbles 0, 1, 4, and 5 in the first Bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble Utilization for 2x32 Interface using SDP, DDP (2 Rank), or 3DS Components (Flipped)

The following figure shows the nibble utilization for a 2x16 interface using SDP, DDP (2 Ranks) or 3DS components in the flipped configuration. DQL and DQR indicate data nibbles for the left and right interfaces respectively. ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively. sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x16 interface all nibbles in the second Bank are free, in addition to the free nibbles in the first Bank.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 2x16 Interface using SDP, DDP (2 Rank), or 3DS Components (Flipped)

The following figure shows the nibble utilization for a 2x24 interface using SDP, DDP (2 Ranks) or 3DS components in the flipped configuration. DQL and DQR indicate data nibbles for the left and right interfaces respectively. ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively. sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x24 interface all nibbles in the second Bank are free, and nibbles 4 and 5 in addition to nibbles 0, 1, 2, and 3 in the first Bank are free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 3. Nibble Utilization for 2x24 Interface using SDP, DDP (2 Rank), or 3DS Components (Flipped)