DDR Basic Tab - DDR Basic Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document_ID
PG313
Release_Date
2026-06-23
Version
1.1 English
The following figure shows the DDR Basic tab.
Figure 1. DDR Basic Tab

Controller Selection
In the DDR Basic tab, use the Controller Type list to select the required controller type.
  • DDR4 SDRAM
  • LPDDR4/4X SDRAM
Clocking
Clock selection provides two options: Memory Clock and System Clock. If you select Memory Clock, a range of values in ps displays for the Input System Clock Period for the provided Memory Clock period.

The opposite happens if you select System Clock. A range of values in ps is available for the Memory Clock Period for the provided System Clock Period. The range of values is determined based on the clocking architecture. For most use cases, it is easier to first set the Input System Clock Period and then select the desired Memory Clock period.

  • Memory Clock Period: Enter or select the desired memory interface clock period. This clock period is half the toggle rate for DDR4 or LPDDR4/4X memory interfaces.
  • Input System Clock Period: Enter or select the required Input System Clock Period. This clock generates the clocking configuration and resulting memory interface options for the DDRMC.
  • System Clock: Three system clock options are available:
    Differential
    Requires a differential clock source. You must place this on a GC input pin in any of the three XPIO banks used by the DDRMC.
    No Buffer
    Requires a differential clock source. As for Differential, but only half of the differential pair is used by the DDRMC. You can use the other half of the differential pair as a clock source for other logic blocks.
    Internal
    Uses the hsm1_ref_clk clock output from the CIPS IP. The HSM1 clock frequency and the Input System Clock frequency must be set to match each other. Use the following Tcl command to enable this output port: 
    set_property -dict [ list CONFIG.PS_PMC_CONFIG { PMC_HSM1_CLK_OUT_ENABLE 1 } ] [ get_bd_cells versal_cips_0 ]
  • Enable Internal Responder: Enables DDR4 or LPDDR4/4X memory device models for simulation.
    • When you uncheck the Enable Internal Responder option, additional pins are exposed at the IP integrator top level. These pins hook up to the memory model provided externally to the AXI NoC IP. This option lets you replace the AMD responder with a third party memory vendor model.
    • When you check the Enable Internal Responder option, the AMD responder is included inside the AXI NoC IP. No additional pins are added at the IP integrator level. To include the pins in simulation, search for u_ddr_responder and add it to the waveform window.