DDR Advanced Tab - DDR Advanced Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document_ID
PG313
Release_Date
2026-06-23
Version
1.1 English

The following figure shows the DDR Advanced tab.

Figure 1. DDR Advanced Generated by Your Tool

Use the DDR Advanced tab to select the required advanced options listed.

2T Timing (DDR4 Only)
Enabled by default for DDR component configurations. For other DDR configurations such as RDIMM/LRDIMM/UDIMM/SODIMM, you can enable or disable this option.
ECC Options
These options are only applicable for ECC enabled designs.
  • Enable Background Scrubbing (DDR4 only): Refer to the ECC Scrubbing section for details. When you enable ECC for LPDDR4, Background Scrubbing is automatically enabled.
  • Initialize Memory for ECC: This option is enabled by default.
  • ECC Initialization Size (MB): You can change the initialization size from the default value.
    Note: You are responsible for initializing memory if memory initialization is disabled.
Refresh Options
  • Enable Refresh and Periodic Calibration Interface: Refer to the Refresh section.
  • Fixed fine Granularity Refresh (DDR4 Only): 1x, 2x, 4x. Fixed Fine Granularity Refresh modes can help reduce refresh protocol overhead in high temperature environments. Refer to vendor data sheets for JESD79-4C for more details.
Power Saving Options
Enter the amount of idle clock cycles before controller places the memory in Power Down mode.
Migration Options
Select this to allow adjustment of CAC pin delays. This is necessary for migration from one device to another in the same package. Enabling this option creates an additional tab: Migration Options.
Startup Options
DDRMC Calibration Status at Startup: The default behavior for the Versal PLM at boot is to gate the assertion of the Configuration DONE signal if a DDRMC fails calibration. If this option is set to SKIP, then the DDRMC calibration status is ignored at startup and DONE asserts regardless of the DDRMC status.