There are four NoC slave ports to access the Memory Controller. The slave ports sort the commands to the appropriate command queue based on their QoS class. An arbiter then pulls commands from the queues based on priority and bandwidth requirements and pushes them to the Memory Controller. The Memory Controller reorders the commands to optimize for efficiency and then sends them to the Physical Layer which handles the DRAM interface timing and sequencing. The controller can be configured to act as two separate memory channels of up to 32-bit data width per channel.
Note: Each DDRMC-NSU supports two traffic classes per read/write
direction. Because traffic class is implemented as Virtual Channels, this also limits
Separate Routing feasibility to a DDRMC-NSU to one set of paths per each traffic
class.
Figure 1. Memory Controller Block Diagram
