Configuring the Memory Controller - Configuring the Memory Controller - 1.1 English - PG313

You can configure the axi_noc IP core to include one or more integrated DDR memory controllers (MCs). In the current release of the tools, you can configure a given axi_noc instance to include 0, 1, 2, or 4 MCs. The MC group appears as a single interleaved memory to all masters connected through the NoC.

In interleave mode, the application sees a single unified block of memory that spans the participating MCs. The NoC supports interleaving across two or four MCs. It automatically chops AXI requests into interleave block sized sub-requests and alternately sends the sub-requests to each of the participating MCs.

If you configure an axi_noc instance for one or more MCs, several additional tabs appear on the Customize IP dialog box:

DDR Basic

Allows the configuration of the controller/PHY mode and the clocking options. The controller type can be either DDR4 or LPDDR4. The clocking options include setting the memory frequency, and the system clock period and mode.

DDR Memory Options

Allows configuration of the following options:

• Memory device options
• Memory density parameters
• JEDEC timing parameters of the external DDR
• Mode register settings

DDR Address Mapping Options

Allows the remapping of system address bits to DDR address bits. The following three predefined mapping choices are available:

• ROW, BANK, COLUMN
• ROW, COLUMN, BANK
• BANK, ROW, COLUMN

In addition to the predefined choices, you can construct a custom mapping of address bits to row, bank, and column bits.

DDR Advanced

Selects the system address regions and options for ECC, refresh, and power saving modes.